Hit ahead hierarchical scalable priority encoding logic and circuits

ABSTRACT

In this invention a hit ahead multi-level hierarchical scalable priority encoding logic and circuits are disclosed. The advantage of hierarchical priority encoding is to improve the speed and simplify the circuit implementation and make circuit design flexible and scalable. To reduce the time of waiting for previous level priority encoding result, hit signal is generated first in each level to participate next level priority encoding, and it is called Hit Ahead Priority Encoding (HAPE) encoding. The hierarchical priority encoding can be applied to the scalable architecture among the different sub-blocks and can also be applied with in one sub-block. The priority encoding and hit are processed completely parallel without correlation, and the priority encoding, hit generation, address encoding and MUX selection of the address to next level all share same structure of circuits.

This application claims the benefit of provisional U.S. Application Ser.No. 60/550,537, entitled “Priority encoding logic and Circuits,” filedMar. 4, 2004, which is incorporated herein by reference in its entiretyfor all purposes.

FIELD OF THE INVENTION

The presentation relates to content addressable memory. In particular,the present invention relates to logic and circuits of priority encodingof match or hit address.

BACKGROUND OF THE INVENTION

In ternary content addressable memory, not every bit in each row arecompared in the searching or comparing process, so some time in onecomparison, there are more than one row matching the input content, itis called multi-hit or match. In multi-hit case, one protocol was madeto select the highest priority address. The logic of selecting thehighest priority address is called priority encoding.

Assume we have {A₀, A₁, . . . A_(n-1)} hit signals from thecorresponding addresses and define A₀ has the highest priority and A_(n)has the lowest priority. Assume some of {A₀, A₁, . . . A_(n-1), A_(n)}are logic “1” and all of the others are logic “0”, the priority encodingkeep the highest priority “1” as “1” and convert all the other “1” into“0”. The logic operation of this transform:

$\begin{matrix} \{ {A_{0},A_{1},{\ldots\mspace{14mu} A_{n - 1}},A_{n}} \}\Longrightarrow\{ {h_{0},h_{1},{\ldots\mspace{14mu} h_{n - 1}},h_{n}} \}  & (1)\end{matrix}$can logically be expressed as:

$\begin{matrix}{h_{0} = A_{0}} & (2) \\{h_{1} = {{\overset{\_}{A}}_{0}*A_{1}}} & \; \\{h_{2} = {{\overset{\_}{A}}_{0}*{\overset{\_}{A}}_{1}*A_{2}}} & \; \\\ldots & \; \\{h_{n} = {{\overset{\_}{A}}_{0}*{\overset{\_}{A}}_{1}*{\overset{\_}{A}}_{2}\mspace{14mu}\ldots\mspace{14mu} A_{n - 1}*{\overset{\_}{A}}_{n}}} & \;\end{matrix}$

Which means only when A₀ to A_(i-1), are all zero, h_(i)=A_(i),otherwise no matter A_(i)=0 or 1, h_(i)=0.

After the priority encoding, the hit address with the highest prioritywill be encoded to the binary address.

If the entry N are large, say 1K to 128K or even 1M, the calculation ofpriority logic (2) will take long time if we use serial logic. So wecome out the inventions which will be described in the following.

SUMMERY OF THE INVENTION

In this invention, we propose a multi-level hierarchical scalablepriority encoding. For example we make 8 entry as one group as firstlevel and 8 first level as a second level, total 64 entry. Then we canmake 8 second level as third level, total 512 entry, and so on. Theadvantage to make hierarchical priority encoding is to improve thespeed, and simplify the circuit implementation and make circuit designflexible and scalable.

To reduce the time of waiting for previous level priority encodingresult, we generate the hit signal first in each level to participatenext level priority encoding, and we call it Hit Ahead Priority Encoding(HAPE) encoding.

The hierarchical priority encoding can be applied to the scalablearchitecture among the different sub-blocks and can also be applied within one sub-block.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention will now be described, by way ofexample only, with reference to the attached Figures, wherein:

FIG. 1 is a block diagram of scalable architecture of CAM with manysub-block in accordance with one embodiment of the present invention.

FIG. 2a is a logic block diagram of hierarchical priority encoding andmatch address binary encoding within one sub-block in accordance withone embodiment of present invention.

FIG. 2b is the and timing diagram in accordance with FIG. 2b of presentinvention.

FIG. 3 is a logic block diagram of hierarchical priority encoding andmatch address binary encoding in higher level or among the differentsub-block and timing diagram in accordance with one embodiment ofpresent invention.

FIG. 4 is the circuit implementation of priority encoding with 8 inputaddress in accordance with one embodiment of present invention.

FIG. 5 is the circuit implementation of the HIT generation logic addressin accordance with one embodiment of present invention.

FIG. 6 is the circuit implementation of binary encoding logic inaccordance with one embodiment of present invention.

FIG. 7 is the circuit implementation of 8 to 1 mux in accordance withone embodiment of present invention.

DETAILED DESCRIPTION OF THE INVENTIONS

To make the priority encoding logic calculation quicker, the entire CAMblock can be divided into 256 block and divided into four quadruple,each quadruple has 8×8=64 block and each block has 8×8=64 entry as shownin FIG. 1 with embodiment 100.

This is just to explain the principle, the entry number of eachsub-block and the number of sub-block can be different. Assume the datapad 110 are equally distributed in four side of the chip. If all of thedata pad 110 are in one side or less than four side, the principle issame.

First step, route all the data signal in each side (only one side aredrawn in the FIG. 1) to the middle point of that side, which is shown asroute 101a in FIG. 1. Second step, route all the data signal to thecenter of the chip shown as route 102a in FIG. 1. Third step, in thecenter point send the data to be compared to both left and right side(only right side path 103a is shown in FIG. 1. Fourth step, send data toeach one of the 8 column both upper part and down part shown as 104a inFIG. 1. Fifth step, the data to be compared are then sent to eachsub-block 120 in each column to perform the comparison with each entryin every sub-block 120. In embedded application, the entry number ofTCAM is not very large. In that case, the data path start from path104a. If only some selected sub-block are searched or compared, the datato be compared will only be sent into those sub-block to save powerconsumption. After comparison with each entry inside each sub-block 120,the first level and second level priority encoding and binary encodingare performed which will be explained in details in FIG. 2, then thepriority encoding in each column 130 among 8 sub-block will be performedas third level priority encoding and the hit address are sent outthrough path 104b. Next step fourth level priority encoding will beperformed among 8 column 130 in each quadruple and the Hit address aresent out through path 103b. Next step the priority encoding will beperformed in the center of chip among four quadruple and the hit addresswill be sent through path 102b. Last step the hit address are sent tothe output pad 110 through path 101b. The priority encoding among upperquadruple and lower part quadruple can be performed together in path103b.

The priority encoding logic calculation block diagram for each 8×8=64entry sub-block 120 are shown in FIG. 2a with embodiment 200a. Each 8entry of 64 entry are grouped together to do hit logic function from 2h0to 2h7 and generate Hit[0] to Hit[7] in block 201. In the same time each8 entry of 64 entry are performed priority encoding logic calculation ineach block from 2p0 to 2p7 of embodiment block 202 to generate P[63:0],then proceed binary encoding from 2e0 to 2e7 in embodiment block 203 togenerate any three bit BA0[2:0] to BA7[2:0] binary address if there is ahit in any 8 bit group. The eight signal of Hit[0] to Hit[7] from block201 will perform priority encoding in block 206 which is logically exactsame as the priority encoding in each 8 entry group from 2p0 to 2p7. ThePriority Hit Ph[7:0] from Hit[0] to Hit[7] will select the 8 to 1 mux204 and select one three bit binary address from BA0[2:0] to BA7[2:0]and become Add1[2:0]. The priority bit of Hit[0] to Hit[7] is binaryencoded in block 207 which is logically same as the binary encodingblock from 2e0 to 2e7 to generate the address: Add1[5:3]. Add1[5:3] andAdd1[2:0] make Add1[5:0]. Hit[0] to Hit[7] further perform the logicfunction in block 2hh which is logically same as any block 2h0 to 2h7and generate the next level Hit1. Both Add1[5:0] and Hit1 will be passedto the next level.

The timing diagram of embodiment 200a is shown in FIG. 2b withembodiment 200b. Assume all the Hit or miss signal from TCAM comparisonA[i] (A[63:0])which is drawn as signal 240 are available in time t₀, thefirst level hit signal Hit[7:0] generated by block 2h0 to 2h7 are drawnas 241 which is available at time t₁. In the same time A[63:0] aredivided into eight group and priority encoded by block 2p0 to 2p7,generating P[0] to P[63] which are drawn as 244 and available at timet₁. The time delay of generating Ph[7:0] which are drawn as 246 and thetime delay of generating.

BA0[2:0] to BA7[2:0] which are drawn as 245 are roughly same and theyare generated in time t₂. So the Binary address Add1[2:0] which aredrawn as 248 are selected by Ph[7:0] from the 8 group address BA0[2:0]to BA7[2:0] through an eight to one MUX 204 without any further delayexcept the delay of MUX itself which is (t₃−t₂), and the addressAdd1[5:3] which are drawn as 247, Add1[2:0] and Add[5:0] which are drawnas 249 are available at time t₃.

So the total delay from A[63:0] available to the output of binary hitaddress Add1[5:0] is about three stage delay(priority 2p0, binaryencoding 2e0 and 8 to 1 MUX 204), where we call each block(2p0, 2e0 and204 etc) as one stage. The delay of Hit1 243 is two stage delay. So theoutput of Hit1 which is available at t₂ which is one stage earlier thanthe output of binary Hit address Add1[5:0] 249 which is available at t₃.Only Hit1 and Add1[5:0] are sent to the next level priority encoding.The entire sub-block are abstracted as symbol 208. The timing delay ofhit, priority encoding, binary encoding and 8 to 1 mux will be analyzedin details.

FIG. 3 is the logic block diagram of priority encoding of higher levelamong the eight group of 64 entry sub-block or among the 8 sub-block inevery column 130 in FIG. 1. The Hit signal Hit1[7:0] which is marked as313 in FIG. 3 are one stage earlier than the binary hit addressAdd10[5:0] to Add17[5:0] which are marked as 314. Eight bit HIT signalof Hit1[7:0] perform priority encoding in block 309, then the priorityhit signal Ph1[7:0] will select Add2[5:0] from the eight input MUX 311.

In the same time Ph1[7:0] are encoded into binary address Add2[8:6] inblock 310. Add2[8:6] and Add2[5:0] make Add2[8:0]. In block 308 eightinput Hit1[7:0] generate Hit2 at time t₃ which is one stage earlier thanBinary hit address Add2[8:0]. From the timing diagram 340 in FIG. 3, thedelay of binary hit address Add1i[5:0] which is signal 314 to Add2[8:0]which is marked as 319 is an 8 to 1 MUX delay which is (t₄−t₃), wherei=0 to 7. In this hierarchical priority design, the delay on each levelis an 8 to 1 MUX delay because the selection signal from the priorityencoding among the hit signals is available one stage earlier and thereis no extra delay to wait for the selection signal.

Another advantage of this hierarchical priority encoding is that thesimplicity of circuit design. We already see that each level shares thesame logic and circuit design. Say, the priority function block 206, 309in each level are same in logic and circuit, which is shown in FIG. 4,embodiment 400.

Embodiment 400 in FIG. 4 is a sample implementation of the prioritylogic equation (2) which can be deduced to equation (3), where n=7.

$\begin{matrix}{h_{0} = A_{0}} & (3) \\{h_{1} = {{{\overset{\_}{A}}_{0}*A_{1}} = \overset{\_}{A_{0} + {\overset{\_}{A}}_{1}}}} & \; \\{h_{2} = {{{\overset{\_}{A}}_{0}*{\overset{\_}{A}}_{1}*A_{2}} = \overset{\_}{A_{0} + A_{1} + \overset{\_}{A_{2}}}}} & \; \\\ldots & \; \\{h_{n} = {{{\overset{\_}{A}}_{0}*{\overset{\_}{A}}_{1}*{\overset{\_}{A}}_{2}\mspace{14mu}\ldots\mspace{11mu}{\overset{\_}{\; A}}_{n - 1}*A_{n}} = \overset{\_}{A_{0} + {A_{1}\mspace{14mu}\ldots}\mspace{11mu} + \; A_{n - 1} + {\overset{\_}{A}}_{n}}}} & \;\end{matrix}$

The equation (3) is implemented as embodiment 400 in FIG. 4. Each linefrom 4y0 to 4y7 connect the drains of a few N transistors and each line4y0 to 4y7 is the output of dynamic NOR logic of N transistor connectedto that line. At the beginning of each cycle, the gate input signals A₀to A₇ and A₀ to A₇ of all the N transistor from 401 to 436 are set tologic zero which turn off all the N transistors and the enable signal enis set to logic zero which makes all the output of NAND gate 445 to 452to logic one and then turn all the output of inverter 453 to 460 intologic zero. The input pch of the P transistors 437 to 444 are set tologic zero and the P transistor 437 to 444 are turned on, which make theline 4y0 to 4y7 connecting to Vdd with low impedance and pre-charge thepotential level of line 4y0 to 4y7 up to Vdd, then the signal pch isturned into Vdd and turn off the P transistors 437 to 444 before theTCAM comparison results A₀ to A₇ and their complementary Ā₀ and Ā₇arrive. The Hit signal among A0 to A7 will be logical “one” at potentialVdd and the missed signal among A0 to A7 will be logical zero atpotential ground. Only the highest priority hit, the output of the NORgates are logically high. For example, A₀=0, A₁=0, A₂=Vdd and A₃=Vdd,the highest priority hit is A₂. The input of N transistor 401 is Vdd andN transistor 401 is turned on and the node 4y0 is discharged to ground.The input of transistor 402 which is the complementary of A₁ is also Vddand the transistor 402 is ON, the node of 4y1 is also discharged toground.

Since A₀=0, A₁=0, A₂=Vdd, Ā₂=0, so the inputs of transistors 404, 405,406 are all zero and the transistor 404, 405, 406 are all OFF and thenode 4y2 will not be discharged and will be kept logically “one” atpotential Vdd. Since A₂=Vdd, the inputs of transistors 408, 413, 419,426 and 434 will be Vdd and all the node 4y3, 4y4, 4y5, 4y6 and 4y7 willbe pulled to ground no matter if A₃, A₄, A₅, A₆ and A₇ are logically oneor zero. The slowest path or worst case is only one input among eight Ntransistor 429, 430, 431, 432, 433, 434, 435 and 436 connected to node4y7 is Vdd and all the others are zero, in that case one transistor needto discharge the drain parasitic capacitance of eight transistor and themetal wire capacitance connected to node 4y7. The signal en ischaracterized to turned to Vdd later then node 4y7 is discharged inworst case. The worst case delay of eight input priority encoding isthat one N transistor discharging the drain parasitic capacitance ofeight same size N transistor down to ground plus the delay of one NANDgate and one inverter.

The logic of Hit function block 2h0, 2h1, . . . 2hh and 308 in eachlevel is also same and its logic and circuit are shown in FIG. 5. Theembodiment 510 is the circuit implementation of one block 2h0 and theembodiment 520 is the circuit implementation of both block 201 and block2hh in FIG. 2a together. The operation principle of 510 is: 1) all theinput A0 to A7 are set to zero as in embodiment 400 in FIG. 4. 2) Setthe gate input 522 of P transistor 501 to zero to pre-charge the node503 to Vdd, then turn 522 to Vdd and turn off the P transistor 501before the signal A0 to A7 arrive. If all the input A0 to A7 are zero,the input of N transistors are zero and all the N transistors 502 areOFF and the node 503 is kept in Vdd and the output signal of inverter504 is zero. If only one input among A0 to A7 is Vdd and all the othersare zero, which is the worst case, the delay of 510 is that one Ntransistor discharge the drain parasitic capacitance of the eight samesize N transistor down to ground plus the delay of one inverter.

The binary encoding logic and circuit is shown as embodiment 600 in FIG.6. The operation principle of 600 is: 1) all the input h₀, h₂, h₄ and h₆are set zero. 2) Set the gate input 611 of P transistor 601 to zero topre-charge the node 603 to Vdd, then turn 611 to Vdd and turn off the Ptransistor 601 before the signal h₀, h₂, h₄ and h₆ arrive. If all theinput signal h₀, h₂, h₄ and h₆ are zero, the input of N transistors arezero and all the N transistors 602 are OFF and the node 603 is kept inVdd and the output signal of inverter 604 is zero. If only one inputamong h₀, h₂, h₄ and h₆ is Vdd and all the others are zero, which is theworst case, the delay of 600 is that one N transistor discharging thedrain parasitic capacitance of the four same size N transistor down toground plus the delay of one inverter.

The MUX logic and circuit is shown in FIG. 7 as embodiment 700. Theoperation principle of 700 is: 1) the input signal Ph₀, Ph₁, Ph₂, Ph₃,Ph₄, Ph₅, Ph₆ and Ph₇ are set zero. 2) Set the gate input 705 of Ptransistor 701 to zero to pre-charge the node 703 to Vdd, then turn 705to Vdd and turn off the P transistor 701 before the signal Ph₀, Ph₁,Ph₂, Ph₃, Ph₄, Ph₅, Ph₆ and P₇ arrive. Since Ph₀, Ph₁, Ph₂, Ph₃, Ph₄,Ph₅, Ph₆ and Ph₇ are from Priority encoding, only one signal among themis Vdd and all the other are zero if there is hit. After AND logic, onlyone output of the seven AND gate 708 is equal to the input value whichis the selected bit from Ba₀ to Ba₇. If the selected bit from Ba₀ to Ba₇is zero, the node 703 is kept Vdd and the output of inverter 704 is zeroand the selected bit value zero is passed out. If the selected bit fromBa₀ to Ba₇ is Vdd, one N transistor among eight N transistor 702 isturned ON and the node 703 is discharged down to ground and the outputof inverter 704 is Vdd(logical one) and the selected bit value Vdd ispassed out, which is the worst case, the delay of 700 is one Ntransistor discharging the drain parasitic capacitance of the eight samesize N transistor down to ground plus the delay of one inverter and oneAND gate. Usually one AND gate includes one inverter and one NAND gate,so the delay of 700 is one N transistor discharging the drain parasiticcapacitance of the eight same size N transistor down to the ground plusthe delay of two inverter and one NAND gate.

The entire Priority encoding logic and circuit are simplified as a fourbasic building block of 400, 510, 600 and 700 in FIGS. 4, 5, 6 and 7.The delay of each block 400, 510, 600 and 700 are comparable and we callthe time of delay of each block 400, 510, 600 and 700 one stage. If wedefine the delay of hit logic block 510 as T_(h), one inverter delay isT_(i) and one NAND gate delay is T_(n). The delay of priority encodingblock 400 is (T_(h)+T_(n)) since the delay of block 400 is one more NANDgate delay comparing with block 510. The delay of block 600 is roughlyT_(h). The delay of MUX block 700 is (T_(h)+T_(n)+T_(i)). The extradelay of each higher level priority encoding is a MUX 700 selectiondelay because that the Hit signal in each priority encoding level isgenerated one stage earlier than the binary hit address and theselection signal of the MUX is already available when the binary addressto be selected arrive and will not suffer extra delay.

The previous description of the disclosed embodiments is provided toenable any person skilled in the art to make or use the presentinvention. Various modifications to these embodiments will be readilyapparent to those skilled in the art, and the generic principles definedherein may be applied to other embodiments without departing from thespirit or scope of the invention. Thus, the present invention is notintended to be limited to the embodiments shown herein but is to beaccorded the widest scope consistent with the principles and novelfeatures disclosed herein.

What is claimed is:
 1. A content address able memory(CAM) and hit aheadpriority encoding(HAPE) logic, comprising: a group of blocks which isarranged in column and row, each block has equal number of CAM matchsignals which are the input signals of priority encoding logic, eachblock has same priority encoding logic of CAM match signals within theblock, the CAM match signals or input signals are arranged from lowerpriority to higher priority or from higher priority to lower priority,each CAM match signals or input signal has either high logic level “one”which is called hit or low logic level “zero” which is called miss, eachblock generates block hit when there is at least one CAM match signal ishigh logic “one” within the block or block miss signal when all the CAMmatch signals are in low logic level “zero” within the block and blockbinary address signal corresponding to the CAM match signals of highestpriority within the block, a priority encoding logic of block hit ormiss signals of each column, each column generates a column hit signalwhen there is at least one block hit signal within the column or columnmiss signal when there is only block miss signals within the column andcolumn binary address corresponding to the CAM match signals of highestpriority within the column, a priority encoding logic of column hit ormiss signals of a group column, a group of column generates a hit signalwhen there is at least one column hit signal within the group column ora miss signal when there is only column miss signals within the groupcolumn and a group column binary address corresponding to the CAM matchsignals of highest priority within the group column.
 2. A contentaddress able memory(CAM) and hit ahead priority encoding(HAPE) logic ofclaim 1, further comprising: a block multiplexer to select the binaryaddress from the block of highest priority hit within the column as lesssignificant portion of the column binary address; and a priorityencoding logic of block hit signals to generate the block multiplexercontrol signal which select the block of highest priority hit within thecolumn, and a binary address encoding logic of block hit signals togenerate the more significant portion of the column highest prioritybinary address.
 3. A content address able memory(CAM) and hit aheadpriority encoding(HAPE) logic of claim 1, wherein each block comprises:a group of sub-blocks, each sub-block has equal number of input signals,each sub-block has priority encoding and binary address encoding logicto generate sub-block highest priority binary address as well as hit ormiss generating logic to generate sub-block hit or miss signal, and thesub-block hit or miss signal is generated independently before sub-blockbinary address; a block hit or miss generating logic to generate blockhit or miss signal and block hit or miss signal is generatedindependently before the block binary address is generated; a sub-blockmultiplexer to select the binary address from the highest prioritysub-block within the block as less significant portion of block binaryaddress; and a priority encoding logic of each sub-block hit signals togenerate the control signal of sub-block multiplexer, and a binaryaddress encoding logic of each sub-block hit signals to generate themore significant portion of block binary address.
 4. A contentaddressable memory(CAM) and hit ahead priority encoding(HAPE) logic ofclaim 3, wherein priority encoding logic, address encoding logic andmultiplexer have the logic circuit of same structure.
 5. A contentaddress able memory(CAM) and hit ahead priority encoding(HAPE) logic ofclaim 4, wherein the hit generating logic, priority encoding logic,address encoding logic and multiplexer have dynamic NOR logic.
 6. Acontent address able memory(CAM) and hit ahead priority encoding(HAPE)logic of claim 2, wherein the signal of controlling the multiplexer isgenerated before or in the same time that the less significant portionof the highest priority local address is generated.
 7. A contentaddressable memory (CAM) and hit ahead priority encoding (HAPE) logic,comprising: a group of blocks which are arranged in columns and rows,each block having an equal number of CAM match signals which are theinput signals of priority encoding logic, each block having a samepriority encoding logic of CAM match signals within the block, the CAMmatch signals or input signals arranged from lower priority to higherpriority or from higher priority to lower priority, each CAM matchsignal or input signal being either a high logic level “one which iscalled hit or a low logic level “zero” which is called miss, each blockconfigured to generate a block hit signal when there is at least one CAMmatch signal that is a high logic level “one” within the block or ablock miss signal when all the CAM match signals are a low logic level“zero” within the block and a block binary address signal correspondingto the CAM match signals of highest priority within the block; apriority encoding logic of block hit or miss signals of each column,each column configured to generate a column hit signal when there is atleast one block hit signal within the column or a column miss signalwhen there are only block miss signals within the column and a columnbinary address corresponding to the CAM match signals of highestpriority within the column; and a priority encoding logic of column hitor miss signals of a group column, the group column configured togenerate a hit signal when there is at least one column hit signalwithin the group column or a miss signal when there are only column misssignals within the group column and a group column binary addresscorresponding to the CAM match signals of highest priority within thegroup column.
 8. The content addressable memory (CAM) and hit aheadpriority encoding (HAPE) logic of claim 7, further comprising: a blockmultiplexer configured to select a binary address from the block havingthe highest priority hit within the column as a less significant portionof the column binary address, the priority encoding logic of block hitsignals being configured to generate a block multiplexer control signalfor selecting the block having the highest priority hit within thecolumn; and a binary address encoding logic of block hit signalsconfigured to generate a more significant portion of the column binaryaddress.
 9. The content addressable memory (CAM) and hit ahead priorityencoding (HAPE) logic of claim 7, wherein each block comprises: a groupof sub-blocks, each sub-block having an equal number of input signals,each sub-block having priority encoding and binary address encodinglogic configured to generate a sub-block highest priority binary addressas well as hit or miss generating logic configured to generate asub-block hit or miss signal, the sub-block hit or miss signal beinggenerated independently before the sub-block binary address; a block hitor miss generating logic configured to generate a block hit or misssignal, the block hit or miss signal being generated independentlybefore the block binary address is generated; a sub-block multiplexerconfigured to select a binary address from a highest priority sub-blockwithin the block as a less significant portion of the block binaryaddress; and a priority encoding logic of each sub-block hit signalsconfigured to generate a control signal of the sub-block multiplexer;and a binary address encoding logic of the sub-block hit signalsconfigured to generate a more significant portion of the block binaryaddress.
 10. The content addressable memory (CAM) and hit ahead priorityencoding (HAPE) logic of claim 9, wherein the priority encoding logic,the address encoding logic, and the multiplexer have logic circuitry ofthe same structure.
 11. The content addressable memory (CAM) and hitahead priority encoding (HAPE) logic of claim 10, wherein the hitgenerating logic, the priority encoding logic, the address encodinglogic, and the multiplexer have dynamic NOR logic.
 12. The contentaddressable memory (CAM) and hit ahead priority encoding (HAPE) logic ofclaim 8, wherein a signal for controlling the multiplexer is generatedbefore or at the same time that the less significant portion of thehighest priority local address is generated.
 13. A content addressablememory (CAM) system, comprising: one or more columns comprising aplurality of circuit segments, at least one of the circuit segmentsconfigured to generate a first circuit segment output based on whetherat least one of a plurality of circuit segment inputs received by the atleast one of the circuit segments corresponds to a first logic level, atleast one of the one or more columns configured to generate firstaddress information based on a selected one of the first circuit segmentoutputs that corresponds to a second logic level, to set a node to athird logic level in response to a first input signal, and tosubsequently change the node to a fourth logic level in response to oneor more of a plurality of second input signals.
 14. The CAM system ofclaim 13, wherein the first circuit segment output represents circuitsegment hit information.
 15. The CAM system of claim 13, wherein the atleast one of the plurality of circuit segment inputs represents matchinformation.
 16. The CAM system of claim 13, wherein the selected one ofthe first circuit segment outputs is a highest priority one of the firstcircuit segment outputs that corresponds to the second logic level. 17.The CAM system of claim 13, wherein: the one or more columns are aplurality of columns, and the plurality of circuit segments are arrangedin the plurality of columns and a plurality of rows.
 18. The CAM systemof claim 13, wherein: the one or more columns are a group of columns;each column in the group configured to generate a column output based onthe first circuit segment output of the at least one of the circuitsegments; and the group configured to generate second addressinformation based on a selected one of the column outputs thatcorresponds to a fifth logic level.
 19. The CAM system of claim 13,wherein: the at least one of the one or more columns is configured topre-charge the node in response to the first input signal; and the atleast one of the one or more columns is configured to subsequentlydischarge the node in response to the one or more of the plurality ofsecond input signals.
 20. The CAM system of claim 13, wherein the firstinput signal is configurable independently of the one or more of theplurality of second input signals.
 21. The CAM system of claim 13,wherein the first logic level and the second logic level are the samelogic level.
 22. The CAM system of claim 13, wherein the one or morecolumns comprise: a first logic circuit configured to generate a firstlogic circuit output based on the selected one of the first circuitsegment outputs that corresponds to the second logic level; a secondlogic circuit configured to generate a second logic circuit output basedon whether the first circuit segment output corresponds to the secondlogic level; and a third logic circuit configured to generate the firstaddress information based on the selected one of the first circuitsegment outputs that corresponds to the second logic level.
 23. The CAMsystem of claim 22, wherein at least one of the first logic circuit, thesecond logic circuit, and the third logic circuit is configured to setthe node to the third logic level in response to the first input signal,and to subsequently change the node to the fourth logic level inresponse to the one or more of the plurality of second input signals.24. The CAM system of claim 22, wherein: the at least one of the circuitsegments is configured to generate a second circuit segment outputrepresenting second address information; and the one or more columnsfurther comprise: a fourth logic circuit configured to select one of thesecond circuit segment outputs as a less significant portion of thefirst address information; and a fifth logic circuit configured togenerate a more significant portion of the first address information.25. The CAM system of claim 24, wherein at least one of the fourth logiccircuit and the fifth logic circuit is configured to set the node to thethird logic level in response to the first input signal, and tosubsequently change the node to the fourth logic level in response tothe one or more of the plurality of second input signals.
 26. Thecontent addressable memory (CAM) system of claim 24, wherein the one ormore columns are each configured to generate a control input for thethird logic circuit before or at the same time when the second circuitsegment output is generated.
 27. The content addressable memory (CAM)system of claim 22, wherein: the plurality of circuit segment inputs isdivided into a plurality of subsets of the circuit segment inputs; andthe first logic circuit comprises: a plurality of fourth logic circuitseach configured to generate a fourth logic circuit output based onwhether at least one of a corresponding subset of the circuit segmentinputs corresponds to the first logic level; and a fifth logic circuitconfigured to generate the first circuit segment output based on whetherat least one of the fourth logic circuit outputs corresponds to thefirst logic level.
 28. The CAM system of claim 27, wherein: at least oneof the fourth logic circuit and the fifth logic circuit is configured toset the node to the third logic level in response to the first inputsignal, and to subsequently change the node to the fourth logic level inresponse to the one or more of the plurality of second input signals;and the fourth logic circuit output is an input to the fifth logiccircuit.
 29. A content addressable memory (CAM) system, comprising: acircuit segment configured to generate a circuit segment output based onwhether at least one of a plurality of circuit segment inputs receivedby the circuit segment corresponds to a first logic level, the circuitsegment configured to set a node to a second logic level in response toan input signal, and to subsequently change the node to a third logiclevel in response to the plurality of circuit segment inputs, thecircuit segment output corresponding to said third logic level.
 30. TheCAM system of claim 29, wherein at least one of the plurality of circuitsegment inputs corresponds to a match line output.
 31. The CAM system ofclaim 29, wherein the circuit segment output represents circuit segmenthit information.
 32. The CAM system of claim 29, wherein at least one ofthe plurality of circuit segment inputs represents match information.33. The CAM system of claim 29, wherein: the circuit segment isconfigured to pre-charge the node in response to the input signal; andthe circuit segment is configured to subsequently discharge the node inresponse to the plurality of circuit segment inputs.
 34. The CAM systemof claim 29, wherein the input signal is configurable independently ofthe plurality of circuit segment inputs.
 35. The CAM system of claim 29,wherein the first logic level and the third logic level are the samelogic level.
 36. The CAM system of claim 29, wherein the circuit segmentis a first circuit segment, and further comprising a second circuitsegment configured to generate address information based on the circuitsegment output.